********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*May 26, 2014
*ECN S14-1149, Rev. B
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si1070X D G S
M1  3  GX S S NMOS W=398935u L=0.25u  
M2  S  GX S D PMOS W=398935u L=0.30u  
RG  G  GX     4.7
R1  D  3      RTEMP 33E-3
CGS GX S      310E-12
DBD S  D      DBD
**************************************************************** 
.MODEL  NMOS        NMOS ( LEVEL  = 3           TOX    = 3E-8
+ RS     = 26E-3           RD     = 0           NSUB   = 2.8E17   
+ kp     = 1.2E-5          UO     = 650             
+ VMAX   = 0               XJ     = 5E-7        KAPPA  = 2E-2
+ ETA    = 1E-4            TPG    = 1  
+ IS     = 0               LD     = 0                             
+ CGSO   = 0               CGDO   = 0           CGBO   = 0 
+ TLEV   = 1               BEX    = -1.5        TCV    = 3E-3
+ NFS    = 0.8E12          DELTA  = 0.1)
**************************************************************** 
.MODEL  PMOS        PMOS ( LEVEL  = 3           TOX    = 3E-8
+NSUB    = 6E16            TPG    = -1)   
**************************************************************** 
.MODEL DBD D (CJO=50E-12 VJ=0.38 M=0.15
+FC=0.1 IS=1E-12 TT=2.89E-8 N=1 BV=30.2)
**************************************************************** 
.MODEL RTEMP R (TC1=7E-3 TC2=5.5E-6)
**************************************************************** 
.ENDS
 
